The present invention relates to a semiconductor device and a method for manufacturing the same.
The packaging density of the semiconductor devices has been increased greatly as in integrated circuits (IC), large scale integration (LSI) and then very large scale integration (VLSI). Along with the increase in the packaging density, fine patterning technologies have been improved. If large scale integration is developed and the number of transistors formed on a single semiconductor substrate increases, an area for electrode wirings between the transistors is increased. Thus, a higher packaging density may not likely be accomplished.
For example, for forming Al electrode wirings, aluminum is deposited on a field region to a thickness of about 1 to 2 .mu.m and is patterned by photoetching to form Al wiring patterns which allow connections between semiconductor elements. Further, in metal silicide wirings which have been recently used, polycrystalline silicon is patterned by photoetching and a metal having a high melting point is deposited on the polycrystalline silicon pattern. The wafer is then annealed at a temperature of 500.degree. to 700.degree. C., to form metal silicide wiring patterns. Alternatively, silicon and the metal with a high melting point are simultaneously vacuum deposited. Thereafter, the metal silicide is patterned to form metal silicide wiring patterns. Otherwise, metal silicide is deposited on the polycrystalline silicon pattern and is patterned by photoetching to form metal silicide wiring patterns. In summary, the wiring patterns are formed by photoetching.
However, in the methods described above, precision of the wiring patterns completely depends upon patterning precision of the photoetching technique. With the currently employed photoetching techniques, a distance between the adjacent wirings of the photoresist pattern is 2.0 .mu.m at best. If electron beam etching is performed, a photoresist patterning provides a minimum isolation distance of 1.0 .mu.m. However, in consideration of the material uniformity and reproducibility of the silicon wafer as well as side etching of electrode films, the distance between the adjacent wirings may be more or less about 2 to 3 .mu.m in practice.